Signal processing systems, especially digital data processing systems, commonly employ a reference time clock through which signal/data processing operations throughout the system are controlled. Because of a variety of factors that influence the timing of events within the system, such as the inherent throughput delay of individual circuit components, propagation delays of signal transmission links and processing cycle times, it is usually necessary to incorporate delay circuits in the system, thereby ensuring proper timing relationships among signal transitions.
Typically, the delay element employed comprises either a passive delay network or some form of monostable delay circuit containing a monostable multivibrator and associated logic circuitry. Because the operational characteristics of the monostable device are inherently dependent upon the electronic parameters of its transistors, the timing characteristics of a given integrated circuit design can be expected to differ among signal processing architectures manufactured during different wafer processing runs. Namely, variations in wafer processing parameters can be expected to produce delay circuits having differing timing characteristics from chip-to-chip.
Another drawback of the conventional monostable delay circuit is its dependency on precise power supply levels. Again, because of the operational sensitivities of the circuit's components (i.e. transistors) to an external influence beyond the control of the system designer, performance (e.g. processing speed) of the architecture is limited.
These two drawbacks (sensitivity to processing parameters and power supply variations) have effectively limited the variety of components that may be included in a library of standard cells or components from which the system designer may select to implement increasingly complex, application-tailored signal processing architectures.